AS7C332MNTD18A Datasheet PDF (3.3V 2M x 18 Pipelined SRAM) | Download Alliance Semiconductor Corporation AS7C332MNTD18A

AS7C332MNTD18A - 3.3V 2M x 18 Pipelined SRAM

Description

The AS7C332MNTD18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 2,097,152 words × 18 bits and incorporates a LATE LATE Write.

Features

Organization: 2,097,152 words × 18 bits.
NTD™ architecture for efficient bus operation.
Fast clock speeds to 200 MHz.
Fast clock to data access: 3.2/3.5/3.8 ns.
Fast OE access time: 3.2/3.5/3.8 ns.
Fully synchronous operation.
Common data inputs and data outputs www. DataSheet4U. com.
Asynchronous output enable control.
Available in 100-pin TQFP package Logic block diagram A[20:0] 21 D.
Byte write enables.

Datasheet Details

Part number	AS7C332MNTD18A
Manufacturer	Alliance Semiconductor Corporation
File Size	484.78 KB
Description	3.3V 2M x 18 Pipelined SRAM
Datasheet	AS7C332MNTD18A Datasheet
Additional preview pages of the AS7C332MNTD18A datasheet.

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Full PDF Text Transcription

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December 2004 ® AS7C332MNTD18A 3.3V 2M × 18 Pipelined SRAM with NTDTM Features • Organization: 2,097,152 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns • Fast OE access time: 3.2/3.5/3.8 ns • Fully synchronous operation • Common data inputs and data outputs www.DataSheet4U.com • Asynchronous output enable control • Available in 100-pin TQFP package Logic block diagram A[20:0] 21 D • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.

Published: Jan 1, 2009 |