AS7C33512PFD18A Description
November 2004 ® AS7C33512PFD18A 3.3V 512K × 18 pipeline burst synchronous SRAM.
AS7C33512PFD18A Key Features
- Organization: 524,288 words × 18 bits
- Fast clock speeds to 166 MHz
- Fast clock to data access: 3.5/4.0 ns
- Fast OE access time: 3.5/4.0 ns
- Fully synchronous register-to-register operation
- Dual-cycle deselect
- Asynchronous output enable control
- Individual byte write and global write
- Available in 100-pin TQFP package
- Linear or interleaved burst control Snooze mode for reduced power-standby mon data inputs and data outputs Byte write en