AS7C33512PFD18A Datasheet | Alliance Semiconductor Corporation

Features - Organization: 524,288 words × 18 bits - Fast clock speeds to 166 MHz - Fast clock to data access: 3.5/4.0 ns - Fast OE access time: 3.5/4.0 ns - Fully synchronous register-to-register operation - Dual-cycle deselect - Asynchronous output enable control .. - Individual byte write and global write - Available in 100-pin TQFP package - - - - - - - Linear or interleaved burst control Snooze mode for reduced power-standby mon data inputs and data outputs Byte write enables Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Logic block diagram CLK ADV ADSC ADSP A[18:0] CLK CS CLR Burst logic 19 17 19 Q D CS Address register CLK 512K × 18 Memory array 18 18 GWE BWb BWE BWa CE0 CE1 CE2 D DQb CLK D DQa Q Byte Write registers Byte Write registers CLK D CE CLK ZZ Enable register Output registers Input registers Power down D Enable Q delay register CLK...