AS7C33512PFS18A Overview
November 2004 ® AS7C33512PFS18A 3.3V 512K × 18 pipeline burst synchronous SRAM.
AS7C33512PFS18A Key Features
- Organization: 524,288 words × 18 bits
- Fast clock speeds to 166 MHz
- Fast clock to data access: 3.5/4.0 ns
- Fast OE access time: 3.5/4.0 ns
- Fully synchronous register-to-register operation
- Single-cycle deselect
- Asynchronous output enable control
- Available in 100-pin TQFP package
- Individual byte write and global write
- Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ 30 mW typi