Datasheet4U Logo Datasheet4U.com

ASM4SSTVF16859 - DDR 13-Bit to 26-Bit Registered Buffer

Description

In the JEDEC defined Registered DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB; therefore, no timing relationship can be guaranteed between the two signals.

Features

  • Differential clock signals. Meets SSTL_2 class II specifications on outputs.
  • www. DataSheet4U. com LVCMOS level at a valid state since VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. Low voltage operation: VDD = 2.3V to 2.7V. Available in 64-pin TSSOP, 64-pin TVSOP, and 56-pin VFQFN packages.
  • Product.

📥 Download Datasheet

Datasheet preview – ASM4SSTVF16859

Datasheet Details

Part number ASM4SSTVF16859
Manufacturer Alliance Semiconductor Corporation
File Size 206.36 KB
Description DDR 13-Bit to 26-Bit Registered Buffer
Datasheet download datasheet ASM4SSTVF16859 Datasheet
Additional preview pages of the ASM4SSTVF16859 datasheet.

📁 Similar Datasheet

  • ASM40 - 40W Ultraminiature Medical Open Frame Switching Power Supplies (Astrodyne Corporation)
  • ASM4106C - VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR (Apuls Intergrated Circuits)
  • ASM4112C - VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR (Apuls Intergrated Circuits)
  • ASM4112CB - VERY LOW-COST VOICE SYNTHESIZER (Apuls Intergrated Circuits)
  • ASM - CRYSTAL CLOCK OSCILLATORS (Abracon Corporation)
  • ASM-7.3728MHZ-E - Crystal Clock Oscillators (Abracon)
  • ASM-xx.xxxxMHZ-D - Crystal Clock Oscillators (Abracon)
  • ASM-xx.xxxxMHZ-E - Crystal Clock Oscillators (Abracon)
  • ASM-xx.xxxxMHZ-F - Crystal Clock Oscillators (Abracon)
  • ASM-xx.xxxxMHZ-L - Crystal Clock Oscillators (Abracon)
Other Datasheets by Alliance Semiconductor Corporation

Full PDF Text Transcription

Click to expand full text
August 2004 rev 2.0 DDR 13-Bit to 26-Bit Registered Buffer ASM4SSTVF16859 off. Note that RESETB should be supported with a Features   Differential clock signals. Meets SSTL_2 class II specifications on outputs.  www.DataSheet4U.com LVCMOS level at a valid state since VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. Low voltage operation: VDD = 2.3V to 2.7V. Available in 64-pin TSSOP, 64-pin TVSOP, and 56-pin VFQFN packages.  Product Description The ASM4SSTVF16859 is a universal 13/26 bit register (D F/F based), designed for 2.3V to 2.
Published: |