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ASM4SSTVF16859 - DDR 13-Bit to 26-Bit Registered Buffer

General Description

In the JEDEC defined Registered DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB; therefore, no timing relationship can be guaranteed between the two signals.

Key Features

  • Differential clock signals. Meets SSTL_2 class II specifications on outputs.
  • www. DataSheet4U. com LVCMOS level at a valid state since VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. Low voltage operation: VDD = 2.3V to 2.7V. Available in 64-pin TSSOP, 64-pin TVSOP, and 56-pin VFQFN packages.
  • Product.

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Datasheet Details

Part number ASM4SSTVF16859
Manufacturer Alliance Semiconductor Corporation
File Size 206.36 KB
Description DDR 13-Bit to 26-Bit Registered Buffer
Datasheet download datasheet ASM4SSTVF16859 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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August 2004 rev 2.0 DDR 13-Bit to 26-Bit Registered Buffer ASM4SSTVF16859 off. Note that RESETB should be supported with a Features   Differential clock signals. Meets SSTL_2 class II specifications on outputs.  www.DataSheet4U.com LVCMOS level at a valid state since VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. Low voltage operation: VDD = 2.3V to 2.7V. Available in 64-pin TSSOP, 64-pin TVSOP, and 56-pin VFQFN packages.  Product Description The ASM4SSTVF16859 is a universal 13/26 bit register (D F/F based), designed for 2.3V to 2.