ASM4SSTVF32852 Overview
The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels except for the LVCMOS RESETB input. Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficient noise margins, whereas the RESETB, an LVCMOS...
ASM4SSTVF32852 Key Features
- Differential clock signals. Supports SSTL_2 class II specifications on inputs and outputs. Low voltage operation
- VDD = 2.3V to 2.7V
- Available in 114 ball BGA package. Industrial temperature range also available