AS4C32M32MD1 Datasheet | Alliance Semiconductor

Feature - 4 banks x 8M x 32 organization - Data Mask for Write Control (DM) - Four Banks controlled by BA0 & BA1 - Programmable CAS Latency: 2, 3 - Programmable Wrap Sequence: Sequential or Interleave - Programmable Burst Length: 2, 4, 8, 16 for Sequential Type 2, 4, 8, 16 for Interleave Type - Automatic and Controlled Precharge mand - Power Down Mode - Auto Refresh and Self Refresh - Refresh Interval: 8192 cycles/64ms - Available in 90-ball BGA - Double Data Rate (DDR) - Bidirectional Data Strobe (DQS) for input and output data, active on both edges - Differential clock inputs CLK and /CLK - Power Supply 1.7V - 1.95V - Drive Strength (DS) Option:Full, 1/2, 1/4, 3/4 - Auto Temperature-pensated Self Refresh (Auto TCSR) - Partial-Array Self Refresh (PASR) Option: Full, 1/2, 1/4, 1/8, 1/16 - Deep Power Down (DPD) mode - Operating Temperature Range - mercial -25°C to 85°C (Extended) - Industrial -40°C to 85°C Description The AS4C32M32MD1 is a four bank mobile DDR DRAM organized as 4 banks x 8M x 32. It achieves high speed data transfer rates by employing a chip architecture that pre-fetches multiple bits and then synchronizes the output data to a system clock. All of the controls, address, circuits are synchronized with the positive edge of an externally sup-plied clock. I/O transactions are possible on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Additionally, the device supports low power saving features like PASR, Auto-TCSR, DPD as well as options for different drive strength. It’s ideally suit-able for mobile application. Table 1. Speed Grade Information Speed Grade - Data rate Clock Frequency 400Mbps (max) 200 MHz (max) CAS Latency 3 t RCD (ns) 15 t RP (ns) Table 2 - Ordering Information for ROHS pliant...