AS4C32M32MD2-25BCN Datasheet | Alliance Semiconductor

FEATURE - Double-data rate architecture; two data transfers per clock cycle - Bidirectional data strobes (DQS, DQS#), These are transmitted/received with data to be used in capturing data at the receiver - Differential clock inputs (CK and CK#) - Differential data strobes (DQS and DQS#) - mands & addresses entered on both positive and negative CK edges; data and data mask referenced to both edges of DQS - 8 internal banks for concurrent operation - Data mask (DM) for write data - Burst Length: 4 (default), 8 or 16 - Burst Type: Sequential or Interleave - Read & Write latency : Refer to Table 47 - Auto Precharge option for each burst access - Configurable Drive Strength - Auto Refresh and Self Refresh Modes - Partial Array Self Refresh and Temperature pensated Self Refresh - Deep Power Down Mode - HSUL_12 patible inputs - VDD1/VDD2/VDDQ : 1.8V/1.2V/1.2V - No DLL : CK to DQS is not synchronized - Edge aligned data output, center aligned data input - Auto refresh duty cycle : - 7.8us for -30 to 85 °C Table 1. Ordering Information Part Number Org AS4C64M16MD2-25BCN 64Mx16 AS4C32M32MD2-25BCN 32Mx32 Temperature mercial -30°C to +85°C mercial -30°C to +85°C Max Clock (MHz) Package 134-ball FBGA 134-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency WL t RCD (ns) t RP (ns) DDR2L-800 400MHz...