AS4C4M16SA - 64M Synchronous DRAM

Table 3.

Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

• Fast access time from clock: 5.4 ns.
• Fast clock rate: 166 MHz.
• Fully synchronous operation.
• AEC-Q100 Compliant.
• Internal pipelined architecture.
• 1M word x 16-bit x 4-bank.
• Programmable Mode registers - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function - Optional drive strength control.
• Auto Refresh and Self Refresh.
• 4096 refresh cycles/32ms.
• Automotive Ambient Temperature:.