Datasheet Summary
AS4C64M16MD2-25BCN AS4C32M32MD2-25BCN
Revision History AS4C64M16MD2-25BCN / AS4C32M32MD2-25BCN 134 ball FBGA PACKAGE
Revision Details Rev 1.0 Preliminary datasheet
Date July. 2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
- 1/129
- Rev.1.0 July 2016
AS4C32M32MD2-25BCN
KEY FEATURE
- Double-data rate architecture; two data transfers per clock cycle
- Bidirectional data strobes (DQS, DQS#), These are transmitted/received with data to be used in capturing data at the receiver
- Differential clock inputs (CK...