AS4C64M8D2-25BAN Datasheet | Alliance Semiconductor

Features - JEDEC Standard pliant - JEDEC standard 1.8V I/O (SSTL_18-patible) - Power supplies: VDD & VDDQ = +1.8V ± 0.1V - AEC-Q100 pliant - Automotive Temperature: TC = -40°C ~105°C - Supports JEDEC clock jitter specification - Fully synchronous operation - Fast clock rate: 400 MHz - Differential Clock, CK & CK# - Bidirectional single/differential data strobe - 4 internal banks for concurrent operation - 4-bit prefetch architecture - Internal pipeline architecture - Precharge & active power down - Programmable Mode & Extended Mode registers - Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5 - WRITE latency = READ latency - 1 t CK - Burst lengths: 4 or 8 - Burst type: Sequential / Interleave - DLL enable/disable - Off-Chip Driver (OCD) - Impedance Adjustment - Adjustable data-output drive strength - On-die termination (ODT) - Ro HS pliant - Auto Refresh and Self Refresh - 8192 refresh cycles / 64ms - Average refresh period 7.8μs @ -40°C ≦TC≦ +85°C 3.9μs @ +85°C＜TC≦ +105°C - 60-ball 8 x 10 x 1.2mm (max) FBGA package - Pb and Halogen Free Overview The 512Mb DDR2 is a high-speed CMOS Double Data-Rate-Two (DDR2), synchronous dynamic random access memory (SDRAM) containing 512 Mbits in a 8-bit wide data I/Os. It is internally configured as a quad bank DRAM, 4 banks x 16Mb addresses x 8 I/Os. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style. Accesses begin with the registration of a Bank Activate mand, and then it is followed by a Read or Write mand. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a programmed number of...