AS4LC1M16E5 - 3V 1M x 16 CMOS DRAM

Product Overview

Alliance Semiconductor

Datasheet Details

Part number	AS4LC1M16E5
Manufacturer	Alliance Semiconductor
File Size	467.96 KB
Description	3V 1M x 16 CMOS DRAM
Datasheet	AS4LC1M16E5 Datasheet
Additional preview pages of the AS4LC1M16E5 datasheet.

Product details

Description

A0 to A9 Address inputs RAS Row address strobe DQ1 to DQ16 Input/output OE Output enable WE Write enable UCAS Column address strobe, upper byte LCAS Column address strobe, lower byte VCC Power VSS Ground Selection guide Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum hyper page mode cycle time Maximum operating current Maximum CMOS standby current Shaded areas indicate a

Features

Organization: 1,048,576 words × 16 bits.
High speed - 50/60 ns RAS access time - 20/25 ns hyper page cycle time - 12/15 ns CAS access time.
Low power consumption - Active: 500 mW max (-60) - Standby: 3.6 mW max, CMOS DQ.
Extended data out.
1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh.
Read-modify-write.
TTL-compatible, three-state DQ.
JEDEC standard package and pinout - 4.

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Published: Nov 24, 2014 |