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AS4LC1M16E5 - 3V 1M x 16 CMOS DRAM

Description

A0 to A9 Address inputs RAS Row address strobe DQ1 to DQ16 Input/output OE Output enable WE Write enable UCAS Column address strobe, upper byte LCAS Column address strobe, lower byte VCC Power VSS Ground Selection guide Maximum RAS access time Maximum column address access time Maximum C

Features

  • Organization: 1,048,576 words × 16 bits.
  • High speed - 50/60 ns RAS access time - 20/25 ns hyper page cycle time - 12/15 ns CAS access time.
  • Low power consumption - Active: 500 mW max (-60) - Standby: 3.6 mW max, CMOS DQ.
  • Extended data out.
  • 1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh.
  • Read-modify-write.
  • TTL-compatible, three-state DQ.
  • JEDEC standard package and pinout - 4.

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Datasheet preview – AS4LC1M16E5

Datasheet Details

Part number AS4LC1M16E5
Manufacturer Alliance Semiconductor
File Size 467.96 KB
Description 3V 1M x 16 CMOS DRAM
Datasheet download datasheet AS4LC1M16E5 Datasheet
Additional preview pages of the AS4LC1M16E5 datasheet.

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Full PDF Text Transcription

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AS4LC1M16E5 ® 3V 1M×16 CMOS DRAM (EDO) Features • Organization: 1,048,576 words × 16 bits • High speed - 50/60 ns RAS access time - 20/25 ns hyper page cycle time - 12/15 ns CAS access time • Low power consumption - Active: 500 mW max (-60) - Standby: 3.6 mW max, CMOS DQ • Extended data out • 1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • Read-modify-write • TTL-compatible, three-state DQ • JEDEC standard package and pinout - 400 mil, 42-pin SOJ - 400 mil, 44/50-pin TSOP II • 3V power supply (AS4LC1M16E5) • 5V tolerant I/Os; 5.
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