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AS4LC256K16E0 Datasheet 3.3v 256k X 16 CMOS Dram (edo)

Manufacturer: Alliance Semiconductor

Overview: .. AS4LC256K16EO ® 3.3V 256K X 16 CMOS DRAM (EDO).

General Description

Address inputs Row address strobe Input/output Output enable Column address strobe, upper byte Column address strobe, lower byte Read/write control Power (3.3V ± 0.3V) Ground I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 AS4LC256K16EO I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 AS4LC256K16EO 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 DataShee LCAS 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE WE VCC GND A3 Vcc A4 GND NC A0 A1 A2 A3 VCC A8 A7 A6 A5 A4 GND Selection guide Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum EDO page mode cycle time Maximum operating current Maximum CMOS standby current tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC2 AS4LC256K16EO-35 35 17 7 7 50 15 70 200 AS4LC256K16EO-45 45 20 10 10 80 17 60 200 AS4LC256K16EO-60 60 25 10 10 100 3

Key Features

  • Organization: 262,144 words × 16 bits.
  • High speed - 45/60 ns RAS access time - 10/12/15/20 ns column address access time - 7/10/10 ns CAS access time.
  • Low power consumption.
  • EDO page mode.
  • 5V I/O tolerant.
  • 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self refresh.
  • Read-modify-write.
  • LVTTL-compatible, three-state I/O.
  • JEDEC standard packages - Active: 280 mW max (AS4LC256K16E.

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