AS4LC256K16E0 Description
V.1.1 Alliance Semiconductor P. 1 of 25 Copyright © Alliance Semiconductor. AS4LC256K16EO ® Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits.
AS4LC256K16E0 Key Features
- Organization: 262,144 words × 16 bits
- High speed
- 45/60 ns RAS access time
- 10/12/15/20 ns column address access time
- 7/10/10 ns CAS access time
- Low power consumption
- EDO page mode
- 5V I/O tolerant
- 512 refresh cycles, 8 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self refresh