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AS4LC256K16E0 - 3.3V 256K X 16 CMOS DRAM (EDO)

Description

Address inputs Row address strobe Input/output Output enable Column address strobe, upper byte Column address strobe, lower byte Read/write control Power (3.3V ± 0.3V) Ground I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 AS4LC256K16EO I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 AS4LC256K16EO 1 2 3 4 5 6 7 8 9 1

Features

  • Organization: 262,144 words × 16 bits.
  • High speed - 45/60 ns RAS access time - 10/12/15/20 ns column address access time - 7/10/10 ns CAS access time.
  • Low power consumption.
  • EDO page mode.
  • 5V I/O tolerant.
  • 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self refresh.
  • Read-modify-write.
  • LVTTL-compatible, three-state I/O.
  • JEDEC standard packages - Active: 280 mW max (AS4LC256K16E.

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Datasheet Details

Part number AS4LC256K16E0
Manufacturer Alliance Semiconductor
File Size 812.87 KB
Description 3.3V 256K X 16 CMOS DRAM (EDO)
Datasheet download datasheet AS4LC256K16E0 Datasheet
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www.DataSheet4U.com AS4LC256K16EO ® 3.3V 256K X 16 CMOS DRAM (EDO) Features • Organization: 262,144 words × 16 bits • High speed - 45/60 ns RAS access time - 10/12/15/20 ns column address access time - 7/10/10 ns CAS access time • Low power consumption • EDO page mode • 5V I/O tolerant • 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self refresh • Read-modify-write • LVTTL-compatible, three-state I/O • JEDEC standard packages - Active: 280 mW max (AS4LC256K16EO-35) - Standby: 2.8 mW max, CMOS I/O (AS4LC256K16EO35) - 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II • 3.
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