ASM5I2304B Datasheet PDF - Alliance Semiconductor 3.3 V Zero Delay Buffer Specs

ASM5I2304B - 3.3 V Zero Delay Buffer

Datasheet Summary

Description

ASM5P2304B is a versatile, 3.3V zero-delay buffer designed to distribute workstation, datacom, telecom and other high-performance applications.

It is available in an 8 pin package.

Features

Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304B Configurations Table”. Input frequency range: 4MHz to 20MHz.
Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. www. DataSheet4U. com.
Multiple low-skew outputs. ASM5P2304B has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL fee.

Datasheet Details

Part number	ASM5I2304B
Manufacturer	Alliance Semiconductor
File Size	396.17 KB
Description	3.3 V Zero Delay Buffer
Datasheet	ASM5I2304B Datasheet
Additional preview pages of the ASM5I2304B datasheet.

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Full PDF Text Transcription

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September 2005 rev 0.5 3.3V Zero Delay Buffer Features Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304B Configurations Table”. Input frequency range: 4MHz to 20MHz Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. www.DataSheet4U.com Multiple low-skew outputs. ASM5P2304B has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 200pS. The ASM5P2304B has two banks of two outputs each.

Published: May 9, 2008 |