ASM5I2308A Datasheet PDF - Alliance Semiconductor 3.3 V Zero Delay Buffer Specs

ASM5I2308A - 3.3 V Zero Delay Buffer

Datasheet Summary

Description

ASM5P2308A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks.

It is available in a 16 pin package.

The part has an on-chip PLL which locks to an input clock presented on the REF pin.

Features

Zero input - output propagation delay, adjustable by capacitive load on FBK input.
Multiple configurations - Refer “ASM5P2308A Configurations “ Table. www. DataSheet4U. com.
Input frequency range: 15MHz to 133MHz ASM5P2308A allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P2308A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guar.

Datasheet Details

Part number	ASM5I2308A
Manufacturer	Alliance Semiconductor
File Size	415.32 KB
Description	3.3 V Zero Delay Buffer
Datasheet	ASM5I2308A Datasheet
Additional preview pages of the ASM5I2308A datasheet.

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Full PDF Text Transcription

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September 2005 rev 1.4 3.3V Zero-Delay Buffer General Features • Zero input - output propagation delay, adjustable by capacitive load on FBK input. • Multiple configurations - Refer “ASM5P2308A Configurations “ Table. www.DataSheet4U.com • Input frequency range: 15MHz to 133MHz ASM5P2308A allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P2308A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700pS. • Multiple low-skew outputs. • • Output-output skew less than 200pS. Device-device skew less than 700pS. The ASM5P2308A is available in five different • Two banks of four outputs, tri-stateable by two select inputs.

Published: May 9, 2008 |