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AD4130-4 - 24-Bit Sigma-Delta ADC

Datasheet Summary

Description

Companion Products4 Specifications 5 ADC and AFE Specifications5 Analog Input Specifications 6 Reference Specifications6 Sensor Biasing Specifications 7 Diagnostics Specifications8 Rejection Specifications 8 Logic Input and Output Specifications10 Power Specifications 10 Timing Specifications 12 Ab

Features

  • Ultra-low current consumption (typical).
  • 32 µA: continuous conversion mode (gain = 128).
  • 5 µA: duty cycling mode (ratio = 1/16).
  • 0.5 µA: standby mode.
  • 0.1 µA: power-down mode.
  • Built-in features for system level power savings.
  • Current saving duty cycle ratio: 1/4 or 1/16.
  • Smart sequencer and per channel configuration minimizes host processor load.
  • Deep embedded FIFO minimizes host processor load (depth of 256 samples).
  • Autonomous FIFO interrupt f.

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Datasheet preview – AD4130-4

Datasheet Details

Part number AD4130-4
Manufacturer Analog Devices
File Size 3.77 MB
Description 24-Bit Sigma-Delta ADC
Datasheet download datasheet AD4130-4 Datasheet
Additional preview pages of the AD4130-4 datasheet.

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Full PDF Text Transcription

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Data Sheet AD4130-4 32 μA, Ultra-Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO FEATURES ► Ultra-low current consumption (typical) ► 32 µA: continuous conversion mode (gain = 128) ► 5 µA: duty cycling mode (ratio = 1/16) ► 0.5 µA: standby mode ► 0.1 µA: power-down mode ► Built-in features for system level power savings ► Current saving duty cycle ratio: 1/4 or 1/16 ► Smart sequencer and per channel configuration minimizes host processor load ► Deep embedded FIFO minimizes host processor load (depth of 256 samples) ► Autonomous FIFO interrupt functionality, threshold detection ► Single supply as low as 1.71 V increasing battery length ► RMS noise: 25 nV rms at 1.17 SPS (gain = 128) − 48 nV/√Hz ► Up to 22 noise free bits (gain = 1) ► Output data rate: 1.17 SPS to 2.
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