Datasheet4U Logo Datasheet4U.com

ADN2865 - Clock and Data Recovery

Datasheet Summary

Description

The ADN2865 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s.

An integrated deserialiser supports 8 bit parallel transfer to an FPGA or digital ASIC.

Features

  • Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds ITU-T Jitter Specifications Integrated Limiting Amp: 6mV sensitivity Adjustable slice level: ±100 mV Patented dual-loop clock recovery architecture Programmable LOS detect and Slice Level Integrated PRBS Generator and Detector No reference clock required Loss of lock indicator Rate Selectivity without the use of a reference clock I2C™ interface to access optional features Single-supply operation: 3.3 V Low power: 1.0W 8 mm × 8 mm 56-lead LFCSP AD.

📥 Download Datasheet

Datasheet preview – ADN2865

Datasheet Details

Part number ADN2865
Manufacturer Analog Devices
File Size 476.54 KB
Description Clock and Data Recovery
Datasheet download datasheet ADN2865 Datasheet
Additional preview pages of the ADN2865 datasheet.

📁 Similar Datasheet

Other Datasheets by Analog Devices
  • ADN2860 - 3-Channel Digital Potentiometer with Nonvolatile Memory
  • ADN2804 - Clock and Data Recovery
  • ADN2805 - 1.25 Gbps Clock and Data Recovery IC
  • ADN2806 - Clock and Data Recovery IC
  • ADN2807 - Clock and Data Recovery
  • ADN2809 - Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
  • ADN2811 - OC-48/OC-48 FEC Clock and Data Recovery IC
  • ADN2812 - Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES Preliminary Technical Data FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds ITU-T Jitter Specifications Integrated Limiting Amp: 6mV sensitivity Adjustable slice level: ±100 mV Patented dual-loop clock recovery architecture Programmable LOS detect and Slice Level Integrated PRBS Generator and Detector No reference clock required Loss of lock indicator Rate Selectivity without the use of a reference clock I2C™ interface to access optional features Single-supply operation: 3.3 V Low power: 1.
Published: |