ADSP-21261 Datasheet | Analog Devices

SHARC Embedded Processor ADSP-21261/ADSP-21262/ADSP-21266 SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Code patibility- at assembly level, uses the same instruction set as other SHARC DSPs Processes high performance audio while enabling low system costs Audio decoders and postprocessor algorithms support nonvolatile memory that can be configured to contain a bination of PCM 96 k Hz, Dolby Digital, Dolby Digital Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMAPRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6 Various multichannel surround sound decoders are contained in ROM. For configurations of decoder algorithms, see Table 3 on Page 4. Single-instruction multiple-data (SIMD) putational architecture- two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point putational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O- a parallel port, an SPI port, 6 serial ports, a Digital application interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and 3 programmable timers, all under software control by the signal routing unit (SRU) On-chip memory- up to 2M bits on-chip SRAM and a dedicated 4M bits on-chip mask-programmable ROM The ADSP-2126x processors are available with a 150 MHz or a 200 MHz core instruction rate. For plete ordering information, see Ordering Guide on Page 45. CORE PROCESSOR TIME R INSTRUCTION CACHE 32 ؋ 48-BIT DAG1 DAG2 8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 32 PROG RAM SEQ UENCER DUAL PORTED MEMORY BLOCK 0 S RAM 1M BIT ROM 2M BIT ADDR DATA DUAL PORTED MEMORY BLO CK 1 S RAM 1M BIT ROM 2M BIT ADDR DATA PM ADDRESS BUS DM ADDRESS BUS 32 32 PROCES SING ELEMENT ( PEX ) PRO CESSING ELEMENT ( PE Y) PX REGI STER JTAG TEST & EMULATION 64 PM DATA...