ADSP-21262 Description
For configurations of decoder algorithms, see Table 3 on Page 4. Single-instruction multiple-data (SIMD) putational architecture two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point putational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O a parallel port, an SPI port, 6 serial ports, a Digital application interface (DAI), and JTAG DAI...