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ADSP-21267 - Preliminary Technical Data

Description

The ADSP-21267 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices' Super Harvard Architecture.

Features

  • At 150 MHz (6.65 ns) core instruction rate, the ADSP-21267 operates at 900 MFLOPS performance whether operating on fixed or floating point data 300 MMACS sustained performance at 150 MHz Code compatibility.
  • At assembly level, uses the same instruction set as other SHARC DSPs Super Harvard Architecture.
  • three independent buses for dual data fetch, instruction fetch, and nonintrusive, zerooverhead I/O 1M Bit on-chip dual-ported SRAM (0.5M Bit in block 0 and 0.5M Bit in block 1) for s.

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Datasheet Details

Part number ADSP-21267
Manufacturer Analog Devices
File Size 510.82 KB
Description Preliminary Technical Data
Datasheet download datasheet ADSP-21267 Datasheet
Additional preview pages of the ADSP-21267 datasheet.

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www.DataSheet4U.com Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Code compatible with all other SHARC DSPs The ADSP-21267 processes high performance audio while enabling low system costs Audio decoders and post processor-algorithms support. Non-volatile memory can be configured to contain a combination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2, Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others. See www.analog.
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