ADSP-21267 Datasheet | Analog Devices

.. Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Code patible with all other SHARC DSPs The ADSP-21267 processes high performance audio while enabling low system costs Audio decoders and post processor-algorithms support. Non-volatile memory can be configured to contain a bination of PCM 96 k Hz, Dolby Digital, Dolby Digital EX2, Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others. See .analog./SHARC for a plete list Single-Instruction Multiple-Data (SIMD) putational architecture- two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating point putational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O - a parallel port, an SPI port, four serial ports, a digital audio interface (DAI) and JTAG test port SHARC® Processor ADSP-21267 DAI incorporates two precision clock generators (PCG), and an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU) On-chip memory- 1M Bit of on-chip SRAM and a dedicated 3M Bits of on-chip mask-programmable ROM The ADSP-21267 is available with a 150 MHz core instruction rate. For plete ordering information, see Ordering Guide on page 43 Figure 1. FUNCTIONAL BLOCK DIAGRAM CORE P ROCE SSO R INSTRUCTION CACHE 32 X 48-BIT DUAL PORTED MEMORY BLOCK 0 S RAM 0.5 MBI T DUAL P ORT ED ME MORY BLOCK 1 S RAM 0.5 MBIT TIMER ROM 1.5 MBIT RO M 1.5 MBI T DAG1 8X4X32 DAG 2 8X 4X32 PROG RAM SEQ UE NCE R ADDR DATA ADDR DATA 32 PM ADDRE SS BUS DM ADDRESS BUS 64 64 P M DATA BUS DM DATA BUS IO D (32) IOA (18) PX REGIS TER P ROCE SSI NG ELEME NT (PE X) PRO CE SSI NG ELEMENT (PEY ) DMA CONTROLLER 2 2 C HA N N ELS GPIO FLAG S/ IRQ /TIMEXP S PI PORT (1) A D D RE SS/ D A TA B U S/ GP IO 16 3 6 JTAG TES T & EMULATIO...