CS2500 Overview
The CS2500 is a system-clocking device incorporating a programmable phase-locked loop (PLL). The hybrid analog/ digital PLL architecture prises a delta-sigma fractional-N analog PLL and a digital frequency-locked loop (FLL). The CS2500 enables frequency synthesis and clock generation from a stable timing reference clock.
CS2500 Key Features
- I²C/SPI control port
- Clock frequency synthesizer incorporating delta-sigma fractional-N analog PLL
- Generates low-jitter 6-75 MHz clock (CLK_OUT) from 8-75 MHz timing reference (REF_CLK_IN)
- Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL
- Generates low-jitter 6-75 MHz clock (CLK_OUT), synchronized to a 50 Hz-30 MHz low-quality or intermittent frequency refe
- Configurable auxiliary clock/status output
- Minimal board space required
- No external analog loop-filter ponents
- Pin-to-pin, register map, and control patible with CS2000 and CS2200
- Single-supply operation at 1.8 V or 3.3 V