B9947 Datasheet | Cypress

Features - - - - - - - - - 160-MHz Clock Support LVCMOS/LVTTL patible Inputs 9 Clock Outputs: Drive up to 18 Clock Lines Synchronous Output Enable Output Three-state Control 350-ps Maximum Output-to-Output Skew Pin patible with MPC947 Industrial Temp. Range: - 40°C to +85°C 32-Pin TQFP Package Description The B9947 is a low-voltage clock distribution buffer with the capability to select one of two LVCMOS/LVTTL patible clock inputs. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL patible. The nine outputs are 3.3V LVCMOS or LVTTL patible and can drive two series terminated 50Ω transmission lines. With this capability the B9947 has an effective fanout of 1:18. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the B9947 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The B9947 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Pin Configuration VSS VDDC Q0 VSS Q1 VDDC Q2 VSS VDD TCLK0 TCLK1 TCLK_SEL SYNC_OE TS# 0 1 VDDC Q0-Q8 32 31 30 29 28 27 26 25 VSS TCLK_SEL TCLK0 TCLK1 SYNC_OE TS# VDD VSS 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 VSS Q3 VDDC Q4 VSS Q5 VDDC VSS .. Cypress Semiconductor Corporation Document #: 38-07078 Rev. - C - 3901 North First Street - San Jose - VSS VDDC Q8 VSS Q7 VDDC Q6 VSS CA 95134 - 408-943-2600 Revised December 22, 2002 Pin Description Pin 3 4 2 11, 13, 15, 19, 21, 23, 26, 28, 30 5 Name TCLK0 TCLK1 TCLK_SEL Q(8:0) SYNC_OE VDDC PWR I/O I, PU I, PU I, PU O I, PU Test Clock Input Test Clock Input Test Clock Select Input. When LOW, TCLK0 is selected. When asserted HIGH, TCLK1 is selected. Clock Outputs Output...