B9948L Datasheet | Cypress

Features - - - - - - - - - - - 160-MHz clock support 2.5V or 3.3V output capability 200-ps maximum output-to-output skew LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL patible inputs 12 clock outputs: drive up to 24 clock lines Synchronous Output Enable Output Three-state control Pin patible with MPC948L Industrial temp. range: - 40°C to +85°C 32-pin TQFP package Description The B9948L is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/ LVTTL patible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL patible. The twelve outputs are 2.5V or 3.3V LVCMOS or LVTTL patible and can drive two series-terminated 50Ω transmission lines. With this capability the B9948L has an effective fanout of 1:24. The outputs can also be three-stated via the threestate input TS#. Low output-to-output skews make the B9948L an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The B9948L also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Pin Configuration VSS Q0 VDDC Q1 VSS Q2 VDDC Q3 32 31 30 29 28 27 26 25 VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL SYNC_OE TS# 0 1 VDDC Q0-Q11 TCLK_SEL TCLK PECL_CLK PECL_CLK# SYNC_OE TS# VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 VSS Q4 VDDC Q5 VSS Q6 VDDC Q7 .. Cypress Semiconductor Corporation Document #: 38-07080 Rev. - C - 3901 North First Street - San Jose Q11 VDDC Q10 VSS Q9 VDDC Q8 VSS - CA 95134 - 408-943-2600 Revised December 21, 2002 Pin...