CY29972 Datasheet | Cypress

3.3 V, 125-MHz Multi-Output Zero Delay Buffer Features - - - - - - - - - - - - Table 1. Frequency Table[1] VC0_SEL FB_SEL2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 FB_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FB_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FVC0 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x Output frequency up to 125 MHz 12 Clock outputs: frequency configurable 350 ps max. output-to-output skew Configurable output disable Two reference clock inputs for dynamic toggling Oscillator or crystal reference input Spread-spectrum-patible Glitch-free output clocks transitioning 3.3 V power supply Pin-patible with MPC972 Industrial temperature range: - 40 °C to +85 °C 52-pin Thin quad flat package (TQFP) package Block Diagram XIN XOUT VCO_SEL PLL_EN REF_SEL D Q TCLK0 TCLK1 TCLK_SEL FB_IN D Q Sync Frz 0 1 Phase Detector LPF VCO 0 1 Sync Frz QA0 QA1 QA2 QA3 QB0 QB1 FB_SEL2 QB2 QB3 MR#/OE Power-On Reset SELA(0,1) SELB(0,1) SELC(0,1) FB_SEL(0,1) SCLK SDATA INV_CLK 2 2 2 2 /4, /6, /8, /10 Sync Pulse Data Generator /2 0 1 /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 Sync Frz QC0 QC1 Sync Frz Sync Frz Sync Frz QC2 QC3 FB_OUT SYNC Output Disable Circuitry Note 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz. ..net Cypress Semiconductor Corporation Document #: 38-07290 Rev. - D - 198 Champion Court - San Jose, CA 95134-1709 - 408-943-2600 Revised June 3, 2011 [+] Feedback Contents...