CY29946 Datasheet | Cypress

2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer 2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer Features - - - - - - - - - - Description The CY29946 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL patible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL patible. The 10 outputs are LVCMOS or LVTTL patible and can drive 50  series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. The CY29946 is capable of generating 1× and 1/2× signals from a 1× source. These signals are generated and retimed internally to ensure minimal skew between the 1× and 1/2× signals. SEL(A:C) inputs allow flexibility in selecting the ratio of 1× to1/2× outputs. The CY29946 outputs can also be three-stated via MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs. 2.5 V or 3.3 V operation 200-MHz clock support Two LVCMOS-/LVTTL-patible inputs Ten clock outputs: drive up to 20 clock lines 1× or 1/2× configurable outputs Output three-state control 250-ps max output-to-output skew Pin-patible with MPC946, MPC9446 Available in mercial and industrial temperature range 32-pin TQFP package Block Diagram TCLK_SEL TCLK0 TCLK1 DSELA /1 R /1 0 1 QA0:2 /2 0 3 QB0:2 1 R /2 DSELB /1 0 1 QC0:3 /2 DSELC MR/OE# ..net Cypress Semiconductor Corporation Document #: 38-07286 Rev. - G - 198 Champion Court - San Jose, CA...