CY29948 Datasheet | Cypress

2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer 2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer Features - - - - - - - - - - - Description The CY29948 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL patible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL patible. The 12 outputs are LVCMOS or LVTTL patible and can drive 50  series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:24. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29948 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The CY29948 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. 2.5 V or 3.3 V operation 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS-/LVTTL-patible inputs 12 clock outputs: drive up to 24 clock lines Synchronous Output Enable Output three-state control 150 ps typical output-to-output skew Pin patible with MPC948, MPC948L, MPC9448 Available in mercial and Industrial temp. range 32-pin TQFP package Block Diagram VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL SYNC_OE TS# 0 1 VDDC Q0-Q11 Pin Configuration Q0 VDDC Q2 VDDC 27 26 VSS Q1 VSS Q3 25 24 23 22 21 20 19 18 17 31 30 TCLK_SEL TCLK PECL_CLK PECL_CLK# SYNC_OE TS# VDD VSS 1 2 3 4 5 6 7 8 29 28 9 10 11 12 13 14 15 16 VSS Q4 VDDC Q5 VSS Q6 VDDC Q7 VSS Q9 VDDC Q10 VDDC Q8 Q11 ..net Cypress Semiconductor Corporation Document Number: 38-07288 Rev. - E -...