CY62147CV25 Datasheet | Cypress

47V CY62147CV25/30/33 Mo BL™ 256K x 16 Static RAM Features - High Speed - 55 ns and 70 ns availability - Voltage range: - CY62147CV25: 2.2V- 2.7V - CY62147CV30: 2.7V- 3.3V - CY62147CV33: 3.0V- 3.6V - Pin patible with CY62147V - Ultra-low active power - Typical active current: 1.5 m A @ f = 1 MHz - - - - - Typical active current: 5.5 m A @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE and OE Features Automatic power-down when deselected CMOS for optimum speed/power cantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is acplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is acplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a plete description of read and write modes. The CY62147CV25/30/33 are available in a 48-ball FBGA package. Functional Description The CY62147CV25/30/33 are high-performance CMOS static RAMs organized as 256K...