CY62177DV20 Datasheet | Cypress

CY62177DV20 Mo BL2™ 32-Mbit (2M x 16) Static RAM Features - - - Very high speed: 70 ns Wide voltage range: 1.7V - 2.2V Ultra low active power - Typical active current: 2 m A at f = 1 MHz - Typical active current: 12 m A at f = f MAX Ultra low standby power Easy memory expansion with CE1, CE2, and OE Features Automatic power down when deselected CMOS for optimum speed and power Offered in 48-ball VFBGA package by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: the device is deselected (CE1HIGH or CE2 LOW); outputs are disabled (OE HIGH); both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH); when a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A20). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 9 for a plete description of read and write modes. For best practice remendations, refer to the Cypress application note AN1064, SRAM System Guidelines. - - - - - Functional Description The CY62177DV20 is a high performance CMOS static RAM organized as 2M words by 16 bits. This device Features advanced circuit design to provide ultra low active...