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CY7B9945V - High-Speed Multi-Phase PLL Clock Buffer

General Description

The CY7B9945V high-speed multi-phase PLL clock buffer offers user selectable control over system clock functions.

Key Features

  • 500 ps max Total Timing Budget (TTB™) window.
  • 24 MHz.
  • 200 MHz input and Output Operation.
  • Low Output-output skew.

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Full PDF Text Transcription for CY7B9945V (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for CY7B9945V. For precise diagrams, and layout, please refer to the original PDF.

CY7B9945V RoboClock® High-Speed Multi-Phase PLL Clock Buffer High-Speed Multi-Phase PLL Clock Buffer Features ■ 500 ps max Total Timing Budget (TTB™) window ■ 24 MHz–200 ...

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Features ■ 500 ps max Total Timing Budget (TTB™) window ■ 24 MHz–200 MHz input and Output Operation ■ Low Output-output skew <200 ps ■ 10 + 1 LVTTL outputs driving 50  terminated lines ■ Dedicated feedback output ■ Phase adjustments in 625 ps/1300 ps steps up to +10.4 ns ■ 3.3 V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable Reference Inputs ■ Multiply or Divide Ratios of 1 through 6, 8, 10, and 12 ■ Individual Output Bank Disable ■ Output High Impedance Option for Testing Purposes ■ Integrated Phase Locked Loop (PLL) with Lock Indicator ■ Low Cycle-cycle jitter (<100 ps peak-peak) ■ 3.3 V Operation ■ Industrial Temper