CY7C1165V18 Overview
QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to pletely eliminate the need to turn around the data bus that is required with mon IO devices.
CY7C1165V18 Key Features
- Supports concurrent transactions 300 MHz to 400 MHz clock for high bandwidth 4-word burst to reduce address bus frequenc