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CY7C1168KV18 Datasheet 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1168KV18/CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.

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Key Features

  • 18-Mbit density (1M × 18, 512K × 36).
  • 550-MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
  • Data valid pin (QVLD) to indicate valid data on the output.
  • Sy.

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