CY7C1218F
Features
- Registered inputs and outputs for pipelined operation
- 32K × 36 mon I/O architecture
- 3.3V core power supply
- 3.3V I/O operation
- Fast clock-to-output times
- 3.5 ns (for 166-MHz device)
- 4.0 ns (for 133-MHz device)
- Provide high-performance 3-1-1-1 access rate
- User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
- Separate processor and controller address strobes
- Synchronous self-timed writes
- Asynchronous output enable
- Offered in JEDEC-standard 100-pin TQFP package
- “ZZ” Sleep Mode Option counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable...
