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CY7C1250KV18 Datasheet 36-mbit Ddr Ii+ Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1248KV18/CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • 36-Mbit density (2M × 18, 1M × 36).
  • 450 MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz.
  • Available in 2.0 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems.
  • Data valid pin (QVLD) to indicate valid data on the output.
  • Synch.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1212F 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F 1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214H 1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1215F 1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1217F 1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1218F 1-Mb (32K x36) Pipelined Sync SRAM
CY7C1218H 1-Mbit (32K x36) Pipelined Sync SRAM

CY7C1250KV18 Distributor