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CY7C1353 - 256Kx18 Flow-Through SRAM

Datasheet Summary

Description

The CY7C1353 is a 3.3V 256K by 18 SynchronousFlow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

  • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F.
  • Supports 66-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for Flow-Through operation.
  • Byte Write capability.
  • 256K x 18 common I/O architecture.
  • Single 3.3V power supply.
  • Fast clock-to-output times.

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Datasheet preview – CY7C1353

Datasheet Details

Part number CY7C1353
Manufacturer Cypress Semiconductor
File Size 187.79 KB
Description 256Kx18 Flow-Through SRAM
Datasheet download datasheet CY7C1353 Datasheet
Additional preview pages of the CY7C1353 datasheet.

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www.DataSheet4U.com 1353 CY7C1353 256Kx18 Flow-Through SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for Flow-Through operation • Byte Write capability • 256K x 18 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 11.0 ns (for 66-MHz device) — 12. 0 ns (for 50-MHz device) — 14.
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