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CY7C1354B - 9-Mb (256K x 36/512K x 18) Pipelined SRAM

This page provides the datasheet information for the CY7C1354B, a member of the CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM family.

Datasheet Summary

Description

The CY7C1354B and CY7C1356B are 3.3V, 256K x 3

Features

  • Pin-compatible and functionally equivalent to ZBT.
  • Supports 225-MHz bus operations with zero wait states.
  • Available speed grades are 225, 200, and 166 MHz.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Fully registered (inputs and outputs) for pipelined op- eration.
  • Byte Write capability.
  • Separate VDDQ for 3.3V or 2.5V I/O.
  • Single 3.3V power supply.
  • Fast clock-to-output t.

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Datasheet preview – CY7C1354B

Datasheet Details

Part number CY7C1354B
Manufacturer Cypress Semiconductor
File Size 471.06 KB
Description 9-Mb (256K x 36/512K x 18) Pipelined SRAM
Datasheet download datasheet CY7C1354B Datasheet
Additional preview pages of the CY7C1354B datasheet.

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Full PDF Text Transcription

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CY7C1354B CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT • Supports 225-MHz bus operations with zero wait states — Available speed grades are 225, 200, and 166 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined op- eration • Byte Write capability • Separate VDDQ for 3.3V or 2.5V I/O • Single 3.3V power supply • Fast clock-to-output times — 2.8 ns (for 225-MHz device) — 3.2ns (for 200-MHz device) — 3.5 ns (for 166-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Available in 100 TQFP, 119 BGA, and 165 fBGA packages • IEEE 1149.
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