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CY7C1354B - 9-Mb (256K x 36/512K x 18) Pipelined SRAM

Download the CY7C1354B datasheet PDF. This datasheet also covers the CY7C1356B variant, as both devices belong to the same 9-mb (256k x 36/512k x 18) pipelined sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The CY7C1354B and CY7C1356B are 3.3V, 256K x 3

Key Features

  • Pin-compatible and functionally equivalent to ZBT.
  • Supports 225-MHz bus operations with zero wait states.
  • Available speed grades are 225, 200, and 166 MHz.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Fully registered (inputs and outputs) for pipelined op- eration.
  • Byte Write capability.
  • Separate VDDQ for 3.3V or 2.5V I/O.
  • Single 3.3V power supply.
  • Fast clock-to-output t.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1356B-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C131AE 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C131E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C136AE 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C136E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1354BV25 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1354CV25 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1354D 9-Mbit (256K x 36) Pipelined SRAM
CY7C135 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1354B CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT • Supports 225-MHz bus operations with zero wait states — Available speed grades are 225, 200, and 166 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined op- eration • Byte Write capability • Separate VDDQ for 3.3V or 2.5V I/O • Single 3.3V power supply • Fast clock-to-output times — 2.8 ns (for 225-MHz device) — 3.2ns (for 200-MHz device) — 3.5 ns (for 166-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Available in 100 TQFP, 119 BGA, and 165 fBGA packages • IEEE 1149.