CY7C136A Overview
Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136,.
CY7C136A Key Features
- True dual-ported memory cells that enable simultaneous reads of the same memory location
- 2K x 8 organization
- 0.65 micron CMOS for optimum speed and power
- High speed access: 15 ns
- Low operating power: ICC = 110 mA (maximum)
- Fully asynchronous operation
- Automatic power-down
- Master CY7C132/CY7C136/CY7C136A[1] easily expands data
- BUSY output flag on CY7C132/CY7C136/CY7C136A; BUSY input on CY7C142/CY7C146
- INT flag for port to port munication (52-Pin PLCC/PQFP versions)
