Datasheet4U Logo Datasheet4U.com

CY7C1413KV18 Datasheet 36-mbit Qdr Ii Sram Four-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1411KV18/CY7C1426KV18 CY7C1413KV18/CY7C1415KV18 36-Mbit QDR® II SRAM Four-Word Burst Architecture 36-Mbit QDR® II SRAM Four-Word Burst.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 333 MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo cl.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1413AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1413BV18 (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1413JV18 (CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C141 1K x 8 Dual-Port Static RAM
CY7C1410AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1410JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1410V18 (CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C1411AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18 (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18 (CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture

CY7C1413KV18 Distributor