CY7C1414AV18 Datasheet | Cypress

CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features - Separate Independent Read and Write data ports - Supports concurrent transactions - 250-MHz clock for high bandwidth - 2-Word Burst on all accesses - Double Data Rate (DDR) interfaces on both Read and Write .. ports (data transferred at 500 MHz) @ 250 MHz - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Two input clocks for output data (C and C) to minimize clock skew and flight-time mismatches - Echo clocks (CQ and CQ) simplify data capture in high-speed systems - Single multiplexed address input bus latches address inputs for both Read and Write ports - Separate Port Selects for depth expansion - Synchronous internally self timed writes - Available in x8, x9, x18, and x36 configurations - Full data coherency, providing most current data - Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD - Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) - Offered in both Pb-free and non Pb-free packages - Variable drive HSTL output buffers - JTAG 1149.1 patible test access port - Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to pletely eliminate the need to “turn-around” the data bus required with mon IO devices. Access to each port is acplished through a mon address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are pletely...