CY7C1414KV18 - 36-Mbit QDR II SRAM Two-Word Burst Architecture
This page provides the datasheet information for the CY7C1414KV18, a member of the CY7C1425KV18 36-Mbit QDR II SRAM Two-Word Burst Architecture family.
Datasheet Summary
Features
Separate independent read and write data ports.
Supports concurrent transactions.
333 MHz clock for high bandwidth.
Two-word burst on all accesses.
Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches.
CY7C1425KV18 CY7C1412KV18 CY7C1414KV18
36-Mbit QDR® II SRAM Two-Word Burst Architecture
36-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems ■ Single multiplexed address input bus latches address inputs
for both read and write ports ■ Separate port selects for depth expansion ■ Synchronou
CY7C1414KV18 Datasheet
