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CY7C1415AV18 - (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture

This page provides the datasheet information for the CY7C1415AV18, a member of the CY7C1413AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture family.

Datasheet Summary

Description

The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

Features

  • Functional.

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Datasheet preview – CY7C1415AV18

Datasheet Details

Part number CY7C1415AV18
Manufacturer Cypress Semiconductor
File Size 760.96 KB
Description (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
Datasheet download datasheet CY7C1415AV18 Datasheet
Additional preview pages of the CY7C1415AV18 datasheet.

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Full PDF Text Transcription

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CY7C1411AV18, CY7C1426AV18 www.DataSheet4U.com CY7C1413AV18, CY7C1415AV18 36-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Functional Description The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support the read operations and the write port has dedicated data inputs to support the write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is through a common address bus.
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