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CY7C1425JV18 Datasheet

(cy7c14xxjv18) Sram 2-word Burst Architecture

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

CY7C1425JV18 Overview

QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations.

CY7C1425JV18 Key Features

  • 4M x 8 CY7C1425JV18
  • 4M x 9 CY7C1412JV18
  • 2M x 18 CY7C1414JV18
  • 1M x 36
  • Supports concurrent transactions 267 MHz clock for high bandwidth 2-word burst on all accesses (data transferred at 534
  • Double Data Rate (DDR) interfaces on both read and write ports
  • Functional Description

More Datasheets from Cypress (now Infineon)

See all Cypress (now Infineon) datasheets

Part Number Description
CY7C1425AV18 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1425KV18 36-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1425V18 (CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C142 2K x 8 Dual-Port Static RAM
CY7C1420AV18 (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1421AV18 1.8V Synchronous Pipelined SRAM
CY7C1422AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

CY7C1425JV18 Distributor