CY7C1425KV18 Overview
CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 36-Mbit QDR® II SRAM Two-Word Burst Architecture 36-Mbit QDR® II SRAM Two-Word Burst.
CY7C1425KV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 333 MHz clock for high bandwidth
- Two-word burst on all accesses
- Double data rate (DDR) Interfaces on both read and write ports
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock
- Echo clocks (CQ and CQ) simplify data capture in high speed
- Single multiplexed address input bus latches address inputs