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CY7C1425V18 Datasheet

(cy7c14xxv18) Sram 2-word Burst Architecture

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

CY7C1425V18 Overview

QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to pletely eliminate the need to “turn-around” the data bus required with mon I/O devices.

CY7C1425V18 Key Features

  • Separate Independent Read and Write data ports
  • Supports concurrent transactions
  • 200-MHz clock for high bandwidth
  • 2-Word Burst on all accesses
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz
  • Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
  • Two output clocks (C and C) accounts for clock skew and flight time mismatching
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • Single multiplexed address input bus latches address inputs for both Read and Write ports

More Datasheets from Cypress (now Infineon)

See all Cypress (now Infineon) datasheets

Part Number Description
CY7C1425AV18 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1425JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1425KV18 36-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C142 2K x 8 Dual-Port Static RAM
CY7C1420AV18 (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1421AV18 1.8V Synchronous Pipelined SRAM
CY7C1422AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

CY7C1425V18 Distributor