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CY7C1462BV25 - 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM

This page provides the datasheet information for the CY7C1462BV25, a member of the CY7C1460BV25 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM family.

Datasheet Summary

Features

  • Pin-compatible and functionally equivalent to ZBT™.
  • Supports 250-MHz bus operations with zero wait states.
  • Available speed grades is 250 MHz.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Fully registered (inputs and outputs) for pipelined operation.
  • Byte Write capability.
  • 2.5 V core power supply.
  • 2.5 V I/O power supply.
  • Fast clock-to-output times.
  • 2.6 ns (for 250-MHz device).
  • Clock enable (CEN) p.

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Datasheet preview – CY7C1462BV25

Datasheet Details

Part number CY7C1462BV25
Manufacturer Cypress Semiconductor
File Size 533.66 KB
Description 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM
Datasheet download datasheet CY7C1462BV25 Datasheet
Additional preview pages of the CY7C1462BV25 datasheet.

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Full PDF Text Transcription

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CY7C1460BV25 CY7C1462BV25 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ❐ Available speed grades is 250 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte Write capability ■ 2.5 V core power supply ■ 2.5 V I/O power supply ■ Fast clock-to-output times ❐ 2.
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