Datasheet Summary
CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
- Pin-patible and functionally equivalent to ZBT™
- Supports 250-MHz bus operations with zero wait states
- Available speed grades are 250 MHz, 200 MHz, and 167 MHz
- Internally self-timed output buffer control to eliminate the need to use asynchronous OE
- Fully registered (inputs and outputs) for pipelined operation
- Byte Write capability
- 2.5-V core power supply
- 2.5-V I/O power supply
- Fast clock-to-output times
- 2.5 ns (for 250-MHz device)
- Clock enable (CEN) pin...