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CY7C1462KVE33 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM

Download the CY7C1462KVE33 datasheet PDF. This datasheet also covers the CY7C1460KV33 variant, as both devices belong to the same 36-mbit (1m x 36/2m x 18) pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Pin-compatible and functionally equivalent to Zero Bus Turnaround (ZBT™).
  • Supports 250-MHz bus operations with zero wait states.
  • Available speed grades are 250, 200, and 167 MHz.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Fully-registered (inputs and outputs) for pipelined operation.
  • Byte write capability.
  • 3.3-V power supply.
  • 3.3-V/2.5-V I/O power supply.
  • Fast clock-to-output time.
  • 2.5 ns (for 250-M.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1460KV33-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1462SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
CY7C1460SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1462KVE25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
CY7C1462KV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
CY7C1462AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
CY7C1462AV33 (CY7C146xAV33) 36-Mbit Pipelined SRAM
CY7C1462BV25 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1460KV33 CY7C1460KVE33 CY7C1462KVE33 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC) 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC) Features ■ Pin-compatible and functionally equivalent to Zero Bus Turnaround (ZBT™) ■ Supports 250-MHz bus operations with zero wait states ❐ Available speed grades are 250, 200, and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully-registered (inputs and outputs) for pipelined operation ■ Byte write capability ■ 3.3-V power supply ■ 3.3-V/2.5-V I/O power supply ■ Fast clock-to-output time ❐ 2.