CY7C1474BV33 Datasheet Text
CY7C1470BV33 CY7C1472BV33 CY7C1474BV33
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
Features
- Pin-patible and functionally equivalent to ZBT™
- Supports 250 MHz bus operations with zero wait states
- Available speed grades are 250, 200, and 167 MHz
- Internally self timed output buffer control to eliminate the need to use asynchronous OE
- Fully registered (inputs and outputs) for pipelined operation
- Byte Write capability
- Single 3.3 V power supply
- 3.3 V/2.5 V I/O power supply
- Fast clock-to-output time
- 3.0 ns (for 250 MHz device)
- Clock Enable (CEN) pin to suspend operation
- Synchronous self timed writes
- CY7C1470BV33,
CY7C1472BV33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV33 available in Pb-free and non-Pb-free 209-ball FBGA package
- IEEE...