CY7C25702KV18 Datasheet | Cypress

CY7C25682KV18 CY7C25702KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features - 72-Mbit density (4M × 18, 2M × 36) - 550 MHz clock for high bandwidth - Two-word burst for reducing address bus frequency - Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz - Available in 2.5 clock cycle latency - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Echo Clocks (CQ and CQ) simplify data capture in high speed systems - Data valid pin (QVLD) to indicate valid data on the output - On-die termination (ODT) feature - Supported for D[x:0], BWS[x:0], and K/K inputs - Synchronous internally self-timed writes - DDR II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH - Operates similar to DDR I Device with 1 cycle read latency when DOFF is asserted LOW - Core VDD = 1.8 V...