GVT71256ZB36 Description
) 1CY7C1357A PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL™ Architecture.
GVT71256ZB36 Key Features
- Zero Bus Latency, no dead cycles between write and read cycles
- Fast clock speed: 133, 117, and 100 MHz
- Fast access time: 6.5, 7.0, 7.5, and 8.0 ns
- Internally synchronized registered outputs eliminate the need to control OE
- Single 3.3V -5% and +5% power supply VCC
- Separate VCCQ for 3.3V or 2.5V I/O
- Single R/W (READ/WRITE) control pin
- Positive clock-edge triggered, address, data, and control signal registers for fully pipelined