CY62167GE Datasheet | Cypress

CY62167G/CY62167GE Mo BL 16-Mbit (1M words × 16-bit/ 2M words × 8-bit) Static RAM with Error-Correcting Code (ECC) 16-Mbit (1M words × 16-bit/2M words × 8-bit) Static RAM with Error-Correcting Code (ECC) Features - Ultra-low standby current - Typical standby current: 5.5 A - Maximum standby current: 16 A - High speed: 45 ns/55 ns - Embedded error-correcting code (ECC) for single-bit error correction - Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V - 1.0-V data retention - Transistor-transistor logic (TTL) patible inputs and outputs - Error indication (ERR) pin to indicate 1-bit error detection and correction - 48-pin TSOP I package configurable as 1M × 16 or 2M × 8 SRAM - Available in Pb-free 48-ball VFBGA and 48-pin TSOP I packages Functional Description CY62167G and CY62167GE are high-performance CMOS, low-power (Mo BL®) SRAM devices with embedded ECC[1]. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62167GE device includes an ERR pin that signals a single-bit error-detection and correction event during a read cycle. To access devices with a single chip enable input, assert the chip enable (CE) input LOW. To access dual chip enable devices, assert both chip enable inputs - CE1 as LOW and CE2 as HIGH. To perform data writes, assert the Write Enable (WE) input LOW, and provide the data and address on the device data pins (I/O0 Product Portfolio through I/O15) and address pins (A0 through A19) respectively. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control byte writes and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. You can access read data on the I/O lines (I/O0 through I/O15). To perform byte accesses, assert the required byte enable signal (BHE or...