CY62167E Datasheet | Cypress

CY62167E Mo BL® 16-Mbit (1 M × 16 / 2 M × 8) Static RAM 16-Mbit (1 M × 16 / 2 M × 8) Static RAM Features - Configurable as 1 M × 16 or as 2 M × 8 SRAM - Very high speed: 45 ns - Wide voltage range: 4.5 V to 5.5 V - Ultra low standby power - Typical standby current: 1.5 µA - Maximum standby current: 12 µA - Ultra low active power - Typical active current: 2.2 m A at f = 1 MHz - Easy memory expansion with CE1, CE2, and OE Features - Automatic power-down when deselected - CMOS for optimum speed and power - Offered in 48-pin TSOP I package Functional Description The CY62167E is a high performance CMOS static RAM organized as 1 M words by 16-bits/2 M words by 8-bits. This device Features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life (Mo BL®) in portable applications. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH, or CE2 LOW, or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: - The device is deselected (CE1 HIGH or CE2 LOW) - Outputs are disabled (OE HIGH) - Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) or - A write operation is in progress (CE1 LOW, CE2 HIGH, and WE LOW) To write to the device, take chip enables (CE1 LOW and CE2 HIGH) and write enable (WE) input LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If byte high enable (BHE) is LOW, then data from the I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take chip enables (CE1 LOW and CE2 HIGH) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified...